Title :
Embedded deterministic test for low cost manufacturing test
Author :
Rajski, Janusz ; Tyszer, Jerzy ; Kassab, Mark ; Mukherjee, Nilanjan ; Thompson, Rob ; Tsai, Kun-Han ; Hertwig, Andre ; Tamarapalli, Nagesh ; Mrugalski, Grzegorz ; Eide, Geir ; Qian, Jun
Author_Institution :
Mentor Graphics Corp., Wilsonville, OR, USA
Abstract :
This paper introduces embedded deterministic test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented.
Keywords :
VLSI; automatic test pattern generation; boundary scan testing; data compression; design for testability; integrated circuit testing; logic testing; production testing; ATPG; DFT; compression algorithm; data volume; design flow; embedded deterministic test; logic test; manufacturing test; scan test; test cost; test coverage; test time; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Costs; Design for testability; Frequency; Graphics; Logic testing; Manufacturing;
Conference_Titel :
Test Conference, 2002. Proceedings. International
Print_ISBN :
0-7803-7542-4
DOI :
10.1109/TEST.2002.1041773
