Title :
Reducing test data volume using LFSR reseeding with seed compression
Author :
Krishna, C.V. ; Touba, Nur A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
A new lossless test vector compression scheme is presented which combines linear feedback shift register (LFSR) reseeding and statistical coding in a powerful way. Test vectors can be encoded as LFSR seeds by solving a system of linear equations. The solution space of the linear equations can be quite large. The proposed method takes advantage of this large solution space to find seeds that can be efficiently encoded using a statistical code. Two architectures for implementing LFSR reseeding with seed compression are described. One configures the scan cells themselves to perform the LFSR functionality while the other uses a new idea of "scan windows" to allow the use of a small separate LFSR whose size is independent of the number of scan cells. The proposed scheme can be used either for applying a fully deterministic test set or for mixed-mode built-in self-test (BIST), and it can be used in conjunction with other variations of LFSR reseeding that have been previously proposed to further improve the encoding efficiency.
Keywords :
VLSI; automatic test pattern generation; boundary scan testing; built-in self test; data compression; mixed analogue-digital integrated circuits; shift registers; system-on-chip; LFSR reseeding; encoding efficiency; fully deterministic test set; functionality; linear equations; linear feedback shift register; lossless test vector compression scheme; mixed-mode built-in self-test; scan cells; seed compression; statistical coding; test data volume reduction; Automatic test pattern generation; Built-in self-test; Encoding; Equations; Hardware; Linear feedback shift registers; Logic testing; Power engineering computing; System testing; Vectors;
Conference_Titel :
Test Conference, 2002. Proceedings. International
Print_ISBN :
0-7803-7542-4
DOI :
10.1109/TEST.2002.1041775