Complete, contactless I/O testing reaching the boundary in minimizing digital IC testing cost

Author

Sunter, Stephen K. ; Nadeau-Dostie, Benoit

fYear

2002

fDate

2002

Firstpage

446

Lastpage

455

Abstract

Embedded test of memory and random logic can enable very low cost ATE to test large, high speed ICs because high quality at-speed tests can be generated onchip. However, it is also necessary to test the DC and AC parameters of the input/output (I/O) circuitry. This paper describes how most I/O pin characteristics can be tested cost-effectively with a variety of novel techniques that exploit the 1149.1 and 1149.4 test standards. The techniques measure VOL/IOL, VOH/IOH, VIH, and VIL at DC, perform at-speed I/O wrap, and test on-chip power rail impedance, all via minimum pin-count (MPC) access. The 1149.4 bus is also suitable, of course, for testing mixed-signal functions. The paper then discusses costs and benefits of MPC testing of high pin-count ICs on a low cost tester to show that testing costs can be reduced to insignificance.

Keywords

automatic test equipment; built-in self test; digital integrated circuits; high-speed integrated circuits; integrated circuit testing; 1149.1 test standard; 1149.4 test standard; A C parameters; DC parameters; I/O circuitry; I/O pin characteristics; at-speed I/O wrap; contactless I/O testing; digital IC testing; embedded test; high quality at-speed tests; high speed ICs; input/output circuitry; low cost ATE; memory; minimum pin-count access; mixed-signal functions testing; on-chip power rail impedance; random logic; Built-in self-test; Chip scale packaging; Circuit faults; Circuit testing; Costs; Digital integrated circuits; Frequency; Integrated circuit testing; Logic testing; Probes;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2002. Proceedings. International

ISSN

1089-3539

Print_ISBN

0-7803-7542-4

Type

conf

DOI

10.1109/TEST.2002.1041794

Filename

1041794