Instruction-level hardware/software partition through DFG exploration

Author

Zhao, Kang ; Bian, Jinian

Author_Institution

Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China

fYear

2011

fDate

8-10 June 2011

Firstpage

55

Lastpage

60

Abstract

To reduce the huge search space when customizing instruction-level accelerators for the application specific instruction-set processor (ASIP), this paper proposes an automated instruction-level hardware/software partition method based on the data flow graph exploration. This method integrates the instruction identification and selection using an iterative improvement strategy. The search space is reduced via considering the performance factors during the identification.

Keywords

application specific integrated circuits; data flow graphs; instruction sets; logic partitioning; multiprocessing systems; DFG exploration; application specific instruction-set processor; data flow graph exploration; instruction identification; instruction level hardware-software partition; instruction selection; instruction-level accelerators; iterative improvement strategy; search space; Algorithm design and analysis; Flow graphs; Hardware; MIMO; Optimization; Parallel processing; Software; ASIP; DFG exploration; Hardware/software partition;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Supported Cooperative Work in Design (CSCWD), 2011 15th International Conference on

Conference_Location

Lausanne

Print_ISBN

978-1-4577-0386-7

Type

conf

DOI

10.1109/CSCWD.2011.5960055

Filename

5960055