What a device interface board really costs: an evaluation of technical considerations for testing products operating in the Gigabit region

Author

Warwick, Thomas P.

Author_Institution

Evaluation & Product Eng. Inc., Melbourne, FL, USA

fYear

2002

fDate

2002

Firstpage

555

Lastpage

564

Abstract

The purpose of this paper is to explore the causes of measurement error relating to the device interface board (DIB or DUT (device under test) board) in both ATE and bench characterization for devices operating over 1 Gigabit. Nearly all test setups for high-speed devices have the same basic features and characteristics. These characteristics combine to degrade both input and output signals (the data eye), especially at very high speeds. Within limits, the degradation is predictable. Therefore, DIB-induced errors can be improved and compensated.

Keywords

automatic test equipment; automatic testing; error compensation; integrated circuit testing; logic testing; measurement errors; very high speed integrated circuits; 1 Gbit/s; ATE; DIB; DIB-induced error compensation; DUT board; Gbit region product testing; bench characterization; data eye; device interface board technical considerations/costs; device under test board; input/output signal degradation; measurement errors; test system drivers; very high-speed device test setups; Capacitance; Circuit noise; Circuit testing; Costs; Crosstalk; Degradation; Dielectric losses; Reflection; System testing; Transmission lines;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2002. Proceedings. International

ISSN

1089-3539

Print_ISBN

0-7803-7542-4

Type

conf

DOI

10.1109/TEST.2002.1041806

Filename

1041806