Jitter testing for multi-Gigabit backplane SerDes - techniques to decompose and combine various types of jitter

The recent trend for broadband backplanes is changing from bus-based architectures to fabric/mesh-based high-speed architectures. Freed from heavy loading effects of a bus, modern backplane serializers and deserializers (SerDes) soared to multi-Gigabit-per-second (Gb/s) rate. The increasing integration density, coupled with the increasing data rate, makes jitter testing more critical than ever However, the techniques for jitter testing of a multi-Gigabit backplane SerDes are different from its long haul transceiver counterparts. As specified in some leading communication standards, such as Gigabit Ethernet, Infiniband, and Fiber Channel, jitter is specified in terms of deterministic jitter (DJ), random jitter (RJ), sinusoidal/periodic jitter (PJ) and total jitter (TJ) - as separate specs. To properly test backplane transceivers to these industrial standards, we need to decompose different kinds of jitter in a jitter measurement, and also generate a signal composed of different kinds of jitter for jitter-tolerance testing. Despite its importance, jitter test equipment suited for backplane SerDes is in its infancy. In this article, we describe, compare, and correlate some existing techniques. The backplane jitter test requirements for the test and measurement industry are defined from an IC test engineering perspective.