• DocumentCode
    2378021
  • Title

    Evaluation of integrated circuit´s design limits

  • Author

    Andonova, Anna V. ; Savov, Dimitar T.

  • Author_Institution
    Dept. of Microelectron., Tech. Univ. of Sofia, Bulgaria
  • Volume
    1
  • fYear
    1998
  • fDate
    6-10 Oct 1998
  • Firstpage
    263
  • Abstract
    This paper presents an approach to evaluate the design limits of integrated circuits. The basis of that approach is a destructive evaluation performed on a small number of test items to measure their design limits. Results from applying it demonstrate that the approach can be quite effective for ALT experiments
  • Keywords
    integrated circuit design; integrated circuit testing; life testing; accelerated life test; design limit; integrated circuit; Application specific integrated circuits; Circuit synthesis; Circuit testing; Integrated circuit testing; Life estimation; Life testing; Manufacturing; Performance evaluation; Predictive models; Stress;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Semiconductor Conference, 1998. CAS '98 Proceedings. 1998 International
  • Conference_Location
    Sinaia
  • Print_ISBN
    0-7803-4432-4
  • Type

    conf

  • DOI
    10.1109/SMICND.1998.732368
  • Filename
    732368
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2378021