Hardware accelerator IP-core for wireless 802.16 MAC

Author

Holisaz, H. ; Shamshiri, S. ; Baharvand, F. ; Fakhraie, S.M.

Author_Institution

Sch. of Electr. & Comput. Eng., Tehran Univ.

fYear

0

fDate

0-0 0

Lastpage

5

Abstract

In IEEE 802.16 standard, the performance of the subscriber station (SS) MAC has to meet the timing constraints for the uplink and downlink transmissions. This requirement implies hardware acceleration of some protocol components through a precise hardware-software partitioning. In this paper, we first model the behavior of the system through high level specification and description language (SDL). After automatic translation of the SDL model into a true C model, a SoPC platform is used for prototype implementation. Analysis and HW/SW partitioning of the generated model is performed to meet 75 Mbps throughput required for OFDM-PHY. The proposed hardware accelerator in this paper has been implemented using a 0.13 mum CMOS technology in order to perform more detailed analysis on the performance of design which is targeted for ASIC applications. Analysis results show efficiency of our proposed design in terms of area and timing while achieving the required throughput on a low-cost embedded-processor based platform

Keywords

CMOS integrated circuits; OFDM modulation; WiMax; access protocols; specification languages; CMOS technology; IEEE 802.16 standard; OFDM-PHY; SoPC platform; hardware accelerator IP-core; orthogonal frequency division multiplexing; specification and description language; subscriber station MAC; wireless 802.16 MAC; Acceleration; CMOS technology; Downlink; Hardware; Performance analysis; Protocols; Prototypes; Semiconductor device modeling; Throughput; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless and Optical Communications Networks, 2006 IFIP International Conference on

Conference_Location

Bangalore

Print_ISBN

1-4244-0340-5

Type

conf

DOI

10.1109/WOCN.2006.1666635

Filename

1666635