DocumentCode :
2378101
Title :
An efficient linear time algorithm for scan chain optimization and repartitioning
Author :
Berthelot, David ; Chaudhuri, Samit ; Savoj, Harnid
Author_Institution :
Magma Design Autom. Inc, Cupertino, CA, USA
fYear :
2002
fDate :
2002
Firstpage :
781
Lastpage :
787
Abstract :
Proposes a linear-time algorithm for post-placement scan chain optimization that works efficiently on large designs and that allows user-specified tradeoffs between runtime and solution quality. This algorithm is also efficiently applied on scan chain partitioning. Presents repartitioning algorithm that takes advantage of the linear-time scan chain optimization algorithm presented in the first part. The idea is simply to connect all the scan flipflops of all the scan chains together in a new chain. Then the algorithm optimizes this new chain and splits it in individual chains of the size of the initial chains. Later it assigns individual chains to their closest scan primary input/output pair.
Keywords :
VLSI; automatic testing; boundary scan testing; flip-flops; logic partitioning; logic testing; sequential circuits; individual chains; linear time algorithm; optimization algorithm; post-placement scan chain; primary input/output pair; repartitioning; scan chain optimization; scan flipflops; user-specified tradeoffs; Algorithm design and analysis; Design optimization; Flip-flops; Heuristic algorithms; Joining processes; Partitioning algorithms; Pins; Polynomials; Testing; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2002. Proceedings. International
ISSN :
1089-3539
Print_ISBN :
0-7803-7542-4
Type :
conf
DOI :
10.1109/TEST.2002.1041831
Filename :
1041831
Link To Document :
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