Validating real-time constraints in embedded systems

Author

Shyamasundar, R.K. ; Aghav, J.V.

Author_Institution

Tata Inst. of Fundamental Res., Mumbai, India

fYear

2001

fDate

2001

Firstpage

347

Lastpage

355

Abstract

There is a growing demand for software tools that can assist in designing, analyzing and validating embedded real-time system applications. ESTEREL, a synchronous language, is widely used in the development of embedded systems and hardware/software codesign. We describe a method that uses timed annotations for ESTEREL programs that makes it possible to predict the timing constraints required to be satisfied by the embedded system. Using the specified annotations and the programming environment of ESTEREL, we describe a method and a tool for validating the concrete realization relative to time-annotated ESTEREL specifications. Also, the method derives time constraints to be satisfied by the concrete architectures for realizing the logical specification. We illustrate the technique with examples as well as the structure of the tool implemented

Keywords

embedded systems; hardware-software codesign; program verification; specification languages; ESTEREL; concrete realization; embedded real-time system applications; embedded systems; hardware/software codesign; logical specification; programming environment; real-time constraint validation; software tools; specified annotations; synchronous language; time constraints; time-annotated ESTEREL specifications; timed annotations; timing constraints; Application software; Concrete; Embedded software; Embedded system; Hardware; Programming environments; Real time systems; Software tools; Time factors; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Dependable Computing, 2001. Proceedings. 2001 Pacific Rim International Symposium on

Conference_Location

Seoul

Print_ISBN

0-7695-1414-6

Type

conf

DOI

10.1109/PRDC.2001.992719

Filename

992719