Test setup simulation - a high-performance VHDL-based virtual test solution meeting industrial requirements

Author

Krampl, Gunter ; Rona, Marco ; Tauber, Hermann

Author_Institution

Infineon Technol. Microelectron. Design Centers Austria GmbH, Villach, Austria

fYear

2002

fDate

2002

Firstpage

870

Lastpage

878

Abstract

Virtual test (VT) allows the debug of mixed-signal test programs and associated test hardware in a simulation environment if (1) a cheap, fast and sufficiently accurate chip model, and (2) a converter software linking test programs to simulators can be made available. This paper presents TSS (test setup simulation), a high-performance VT solution based on pure VHDL modeling of the hardware involved, a VHDL-based virtual tester concept and a snapshot test data extractor linking the test program to a simulator together with VT results for a complex telecom device.

Keywords

automatic test equipment; circuit simulation; hardware description languages; hybrid simulation; integrated circuit modelling; integrated circuit testing; mixed analogue-digital integrated circuits; program debugging; virtual instrumentation; ATE; TSS; VT; accurate chip models; high-performance VHDL-based virtual test; mixed-signal test program debug; mixed-signal test setup simulation; pure VHDL hardware modeling; snapshot test data extractor; test hardware debug; test program/simulator linking converter software; virtual tester; Circuit simulation; Circuit testing; Costs; Crosstalk; Debugging; Design engineering; Hardware; Joining processes; Manufacturing; Software testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2002. Proceedings. International

ISSN

1089-3539

Print_ISBN

0-7803-7542-4

Type

conf

DOI

10.1109/TEST.2002.1041841

Filename

1041841