DocumentCode
2378406
Title
Efficient design of system test: a layered architecture
Author
Baldini, Andrea ; Benso, Alfredo ; Prinetto, Paolo ; Mo, Sergio ; Taddei, Andrea
Author_Institution
Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
fYear
2002
fDate
2002
Firstpage
930
Lastpage
939
Abstract
Starting from the idea of a general methodology to transform design specifications into system level functional test patterns for complex embedded systems, we propose a layered architecture as basis of such process. The architecture aims at strongly simplifying the test design, allowing the test engineer to concentrate on the high level parts of the system and wrapping all the complexity of the test environment. The results are then verified on a complex case study of automotive applications.
Keywords
automatic test pattern generation; embedded systems; high level synthesis; logic testing; automotive applications; complex embedded systems; design specifications; high level parts; layered architecture; system level functional test patterns; system test; test environment; Automotive applications; Computer architecture; Design methodology; Embedded software; Embedded system; International collaboration; Magnetic materials; Research and development; System testing; Unified modeling language;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2002. Proceedings. International
ISSN
1089-3539
Print_ISBN
0-7803-7542-4
Type
conf
DOI
10.1109/TEST.2002.1041848
Filename
1041848
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