Electrical through-wafer interconnects with sub-picofarad parasitic capacitance [MEMS packaging]

This paper presents a technology for high density and low parasitic capacitance electrical through-wafer interconnects to an array of capacitive micromachined ultrasonic transducers (CMUTs) on a silicon wafer. Vertical wafer feedthroughs (interconnects) connect an array of sensors or actuators from the front side (transducer side) to the backside (packaging side) of the wafer. A 20 to 1 high aspect ratio 400 μm long and 20 μm diameter interconnect is achieved by using deep reactive ion etching (DRIE). Reduction of the parasitic capacitance of the polysilicon pads to the substrate can be achieved by using reversed-biased pn-junction diodes operating in the depletion region. A parasitic capacitance of 0.3 pF has been achieved by this means. This three-dimensional architecture allows for elegant packaging through simple flip-chip bonding of the chip´s back side to a printed circuit board (PCB) or a signal processing wafer