Global dynamic FET model for GaN transistors: DynaFET model validation and comparison to locally tuned models

Extensive results are presented validating a recently enhanced large signal FET model, DynaFET, applied to an advanced 6×75um periphery, 0.5um gate-length GaN HFET transistor, manufactured by RFMD. Excellent results are achieved for DC (including leakage current), S-parameters versus frequency and temperature, harmonic and intermodulation distortion, as well as load-pull figures of merit, over a very wide range of bias conditions, complex loads, powers, and frequencies. The DynaFET model features detailed dynamic trapping and de-trapping mechanisms for gate and drain lag, and dynamic self-heating. The multi-variate constitutive relations are represented by artificial neural networks (ANNs) trained from large-signal waveform data obtained using an active source injection NVNA-based characterization procedure. The new model is compared with two empirical models, each independently extracted from pulsed I-V data from different quiescent bias points and tuned for specific applications. The DynaFET model is demonstrated to have a much better fit than each of the individually tuned models, even at the tuned conditions. The new global model is sufficiently accurate over the entire operating range of the device that no tuning of model parameters is required for different operating points or amplifier classes of operation. The model runs in transient, harmonic balance, envelope, and all other simulation modes.