Adapting an SoC to ATE concurrent test capabilities

Author

Dorsch, Rainer ; Rivera, Ramdn Huerta ; Wunderlich, Hans-Joachim ; Fischer, Martin

Author_Institution

Comput. Archit. Lab, Stuttgart Univ., Germany

fYear

2002

fDate

2002

Firstpage

1169

Lastpage

1175

Abstract

Concurrent test features are available in SoC testers to increase ATE throughput. To exploit these new features, design modifications are necessary. In a case study, these modifications were applied to the open source LEON SoC platform containing an embedded 32 bit CPU, an AMBA bus, and several embedded cores. The concurrent test of LEON was performed on an SoC tester. The gain in test application time and area costs are quantified and obstacles in the design flow for concurrent test are discussed.

Keywords

automatic test equipment; circuit CAD; integrated circuit design; integrated circuit testing; system-on-chip; 32 bit; AMBA bus; ATE compatible SoC adaption; ATE concurrent test capabilities; ATE throughput; EDA tools; SoC testers; concurrent test design flow; embedded CPU; embedded cores; modification area costs; open source LEON SoC platform; system-on-chip design modifications; test application time; test resource partitioning; Automatic testing; Built-in self-test; Computer architecture; Costs; Frequency; Guidelines; Performance evaluation; System testing; System-on-a-chip; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2002. Proceedings. International

ISSN

1089-3539

Print_ISBN

0-7803-7542-4

Type

conf

DOI

10.1109/TEST.2002.1041875

Filename

1041875