Title :
Si Tunneling Field Effect Transistor with Tunnelling In-Line with the Gate Field
Author :
Fischer, I.A. ; Hähnel, D. ; Isemann, H. ; Kottantharayil, A. ; Murali, G. ; Oehme, M. ; Schulze, J.
Author_Institution :
Inst. for Semicond. Eng., Univ. of Stuttgart, Stuttgart, Germany
Abstract :
As scaling of complementary metal-oxide-semiconductor (CMOS) technology approaches its end, new device concepts are intensively being explored. The tunneling field effect transistor (TFET) is a device proposal that has the potential to outperform CMOS technology both in energy efficiency and speed. This concept, however, has to be improved in such a way that on-currents ION are raised to meet industry requirements while maintaining low off-currents IOFF as well as achieving a subthreshold swing that is below the CMOS limit of 60 mV/dec.
Keywords :
MOSFET; elemental semiconductors; silicon; tunnelling; CMOS technology; Gate Field; Si; TFET; Tunnelling In-Line; complementary metal-oxide-semiconductor technology; energy efficiency; low off-current; tunneling field effect transistor; CMOS integrated circuits; Doping; Etching; FETs; Logic gates; Silicon; Tunneling;
Conference_Titel :
Silicon-Germanium Technology and Device Meeting (ISTDM), 2012 International
Conference_Location :
Berkeley, CA
Print_ISBN :
978-1-4577-1864-9
Electronic_ISBN :
978-1-4577-1863-2
DOI :
10.1109/ISTDM.2012.6222411
