DocumentCode
2378873
Title
Configurable rectilinear Steiner tree construction for SoC and nano technologies
Author
Jiang, Iris Hui-Ru ; Yu, Yen-Ting
Author_Institution
Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu
fYear
2008
fDate
12-15 Oct. 2008
Firstpage
34
Lastpage
39
Abstract
The rectilinear Steiner minimal tree (RSMT) problem is essential in physical design. Moreover, the variant constraints for fabrication issues, including obstacle avoidance, multiple routing layers, layer-specific routing directions, cannot be ignored during RSMT construction for modern SoC and nano technologies. This paper proposes a construction-by-correction approach for obstacle-avoiding preferred direction rectilinear Steiner tree construction. Experimental results show that our algorithm is promising and outperforms the state-of-the-art works.
Keywords
nanoelectronics; network routing; system-on-chip; trees (mathematics); obstacle avoidance; rectilinear Steiner tree construction; routing layers; system-on-chip; Costs; Design engineering; Fabrication; Iris; Large-scale systems; Pins; Routing; Runtime; Steiner trees; Tree graphs;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design, 2008. ICCD 2008. IEEE International Conference on
Conference_Location
Lake Tahoe, CA
ISSN
1063-6404
Print_ISBN
978-1-4244-2657-7
Electronic_ISBN
1063-6404
Type
conf
DOI
10.1109/ICCD.2008.4751837
Filename
4751837
Link To Document