Abstract :
Summary form only given. The test access port (TAP) and associated controller, standardized in IEEE std. 1149.1, is often used to control a wide variety of functions. For example, several existing cores use the TAP and associated controller to control internal test (e.g. logic-BIST) and debug (e.g. scan dumping) functionality. It is also common to see multiple of these cores, each with their own TAP controller, integrated on a single system chip. When this happens, a means of chip-level access needs to be created to be able to use each TAP controller to test or debug the corresponding core. Preferably we do not want to introduce a separate TAP port on the system chip for each internal TAP controller as this can quickly lead to an excessive number of device pins dedicated for test and debug, which is very costly. A solution to this problem is presented elsewhere in this conference as "IEEE 1149.1 $compliant access architecture for multiple-core debug on digital system chips", by Vermeulen, Waayers, and Bakker (Proc. ITC 2002, p. 55, 2002). A summary is given of the reasons why this particular multi-TAP architecture has been standardized within Philips Semiconductors.
Keywords :
IEEE standards; built-in self test; digital integrated circuits; integrated circuit testing; logic testing; peripheral interfaces; system-on-chip; IC testing; IEEE 1149.1 compliant access architecture; TAP chip-level access; debug; internal TAP controllers; internal test control; logic-BIST; multi-TAP architecture; multiple core digital system chips; multiple test access port core debug architecture; multiple-core debug; scan dumping; system chip; test dedicated device pins; Control systems; Digital systems; Pins; System testing;
