IC mixed-signal BIST: separating facts from fiction

Summary form only given. BIST, by definition, requires on-chip generation of the stimulus, and on-chip analysis of the response, sufficient to produce a pass/fail result or a series of bits that any tester can compare bit-wise to the expected bit values. Many so-called on-chip mixed-signal built-in self-test (MS-BIST) approaches in fact require the ATE to supply the stimulus (analog waveform, or sigma-delta bit stream), or perform some response analysis (DSP, histogram processing, or RMS calculation), especially when >10 bits linearity is being tested. For MS-BIST to be technically and economically successful, it must test all key parameters, at-speed, in a test time comparable to that of mixed-signal ATE, with less than 1-2K gates, and permit new types of tests (and higher accuracy tests) to be added post-silicon -presently this is only available in fiction. For MS-BIST to become fact, it will have to evolve gracefully and gradually from partitioned test resources. New DFT and test methods that minimize on-chip circuitry will be implemented first, and then the on-chip portion will increase as each component of the test circuitry and method is proven in production.