A 1.3 GSample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces

Author

Tierno, J. ; Rylyakov, A. ; Rylov, S. ; Singh, M. ; Ampadu, P. ; Nowick, S. ; Immediato, M. ; Gowda, S.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

60

Abstract

A 6 b 10-tap digital FIR filter has a self-timed datapath, clocked interfaces, and variable latency. The architecture of the filter is full rate, distributed arithmetic with signed-digit offset binary (SDOB) number representation. The 0.45 mm/sup 2/ circuit, in 0.18 μm CMOS technology, is operational from 1.2 V to 2.1 V power supply, and has 80 mW dissipation at 300 MSample/s and 4 cycles of latency, and 500 mW at 1.3 GSample/s and 7 cycles of latency.

Keywords

CMOS digital integrated circuits; FIR filters; digital filters; distributed arithmetic; high-speed integrated circuits; 0.18 micron; 1.2 to 2.1 V; 10-tap FIR filter; 6 bit; 80 to 500 mW; CMOS technology; SDOB number representation; clocked interfaces; digital FIR filter; dynamic logic datapath; finite impulse response filter; full-rate distributed-arithmetic architecture; independent precharge; self-timed datapath; signed-digit offset binary number representation; variable latency FIR filter; Arithmetic; Circuits; Clocks; Decoding; Delay; Finite impulse response filter; Latches; Logic; Pipelines; Pulse generation;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.992938

Filename

992938