VLSI models of network-on-chip interconnect

We use VLSI circuit models to analyze the relative delay of interconnect subsystems for networks-on-chips (NoCs). Most work in NoCs has selected a network topology based on higher-level performance models, such as packet delay. Our model parameterizes the interconnect subsystem size by N, the number of IP cores (processors, memories, etc.) to be connected. This paper analyzes busses, crossbars, and some multi-stage networks. We compare the delay required transfer a specific amount of information (bits) between two cores. Considering the data transfer parallelism in crossbars, we make 2 different comparisons: (i) transfer between 2 devices, and (ii) parallel transfers between all devices.