High Performance FDSOI MOSFETs and TFETs Using SiGe Channels and Raised Source and Drain

The interest of the Dual Channel CMOS integration scheme, which features SiGe channels for p-type and Si channels n-type MOSFETs, has conclusively been demonstrated for bulk, FinFET and FDSOI structures. This approach enables to maximize the carriers mobility (μ_e,Si & μ_h,SiGe) and obtain low threshold voltages V_th,p with a single gate stack (because of the SiGe/Si valence band offset). Figure 1 shows a successful integration of sSOI nFETs with cSi_0.6Ge_0.4/s SOI pFETs. The Dual Channel was obtained thanks to a SiO₂ hard mask and selective epitaxy. Specifically, after a <;<;HF-last>;>; wet cleaning and a (800°C, 2 min) H₂ bake, Si_cap/cSiGe stacks with various Ge contents (20%, 40% and 60%) were selectively grown at 20 Torr thanks to a chlorinated chemistry in the pFET active regions (nFET regions covered by SiO2 at this stage). SiGe growth temperatures were reduced from 650°C (xGe=20%) down to 550°C (xGe=40% and 60%) and a dedicated Si capping procedure used in order to minimize surface roughening. The threshold voltages of cSiGe/(s)SOI pMOSFETs are shifted compared to SOI references (+400 to +500mV, due to the SiGe valence band offset, interface states D_it and possible fixed charges Q_f in the gate stack). This V_th,p adjustment at a low value (Vth,p≈-0.2V) contributes to an ID boost with cSiGe/(s)SOI compared to SOI. However, the thick channel stacks (~19nm) leads here to large Short Channel Effects (SCE) and Drain Induced Barrier Lowering. Long channel sSOI nFETs feature a +106% increase in electron mobility compared to SOI at Eeff=0.6 MV/cm. The hole mobility gain at 0.6MV/cm increases with the Ge content, up to +92% for cSi_0.6Ge_0.4/SOI (Figure 2). The extracted low-field mobility μ₀ is degraded as the gate shrinked (20nm) for all types o- channels, all the more so for SiGe channels (the enhancement w.r.t. SOI drops to 0-30% only). This suggests a relaxation of the strain, which is confirmed by Dark Field Electron Holography (Figure 3) and Nano-Beam Eelectron Diffraction. This relaxation is partially due to the Si Raised Source and Drain (RSD) process used here.