Title :
200-mm CVD Grown Si/SiGe Resonant Interband Tunnel Diodes Optimized for High Peak-to-Valley Current Ratios
Author :
Ramesh, Anisha ; Berger, Paul R. ; Douhard, Bastien ; Vandervorst, Wilfried ; Loo, Roger
Author_Institution :
Dept. of Electr. & Comput. Eng., Ohio State Univ., Columbus, OH, USA
Abstract :
Negative differential resistance (NDR) devices in conjunction with MOS transistors will provide a high speed, low power alternate to complementary metal oxide semiconductor (CMOS) technology [1]. Boolean logic with gate-level pipelining has been demonstrated using monostable-bistable logic (MOBILE) gates [1]. Application to low-power embedded memory is also promising [2]. A key hurdle for tunneling based devices is development of a manufacturable process that can be integrated into a CMOS process line. Monolithic integration of low-temperature molecular beam epitaxy (LT-MBE) grown Si/SiGe resonant interband tunnel diodes (RITD) with NMOS [3] has been demonstrated. However, chemical vapor deposition (CVD) is the dominant epitaxial growth technique for semiconductor manufacturing. The first CVD grown Si/SiGe RITD was demonstrated with a peak-to-valley current ratio (PVCR) of 1.85 [4]. In this work, further optimization of boron δ-doping has resulted in high PVCR up to 5.2. Current density dependence on tunneling barrier thickness is also investigated.
Keywords :
CMOS integrated circuits; Ge-Si alloys; chemical vapour deposition; current density; low-power electronics; molecular beam epitaxial growth; monolithic integrated circuits; negative resistance; resonant tunnelling diodes; semiconductor device manufacture; semiconductor doping; Boolean logic; CMOS process line; CMOS technology; CVD; LT-MBE; MOBILE gates; MOS transistor; NDR device; NMOS; PVCR; RITD; Si-SiGe; chemical vapor deposition; complementary metal oxide semiconductor; current density; doping; epitaxial growth; gate-level pipelining; high peak-to-valley current ratio; low-power embedded memory; low-temperature molecular beam epitaxy; manufacturable process; monolithic integration; monostable-bistable logic; negative differential resistance; resonant interband tunnel diodes; semiconductor manufacturing; size 200 mm; tunneling barrier thickness; tunneling based device; Boron; Current density; Logic gates; Silicon; Silicon germanium; Tunneling; Voltage measurement;
Conference_Titel :
Silicon-Germanium Technology and Device Meeting (ISTDM), 2012 International
Conference_Location :
Berkeley, CA
Print_ISBN :
978-1-4577-1864-9
Electronic_ISBN :
978-1-4577-1863-2
DOI :
10.1109/ISTDM.2012.6222481