DocumentCode :
2380118
Title :
AC-coupling strategy for high-speed transceivers of 10Gbps and beyond
Author :
Yikui Dong ; Howard, Steve ; Zhong, Freeman ; Lowrie, Scott ; Paradis, Ken ; Kolnik, Jan ; Burleson, Jeff
Author_Institution :
LSI Logic Corp., Milpitas, CA 95035 USA
fYear :
2007
fDate :
15-17 Oct. 2007
Firstpage :
84
Lastpage :
87
Abstract :
AC coupling in a transmission link is preferred and often required for the functioning of high speed transceivers. But at data rate of 1OGbps and beyond, both the external AC coupling and the conventional on-chip AC coupling approaches bring in heavy burden that pushes to the fundamental limits and are difficult to afford. This paper examines the AC-coupling methods for multi-Gb/s transceivers, and points out the impairments in the existing implementations. A hybrid structure offering both the signal-bump and the AC-capacitor functions under the stringent return-loss requirements of a 1OGb/s+ I/O is proposed and implemented in 65nm standard CMOS. A sizeable 5.1pF AC capacitor is measured with ultra low parasitic expense ratio of less than 120fF.
Keywords :
Backplanes; Capacitors; Couplings; Large scale integration; Logic; Parasitic capacitance; Reflection; Transceivers; Transmitters; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Very Large Scale Integration, 2007. VLSI - SoC 2007. IFIP International Conference on
Conference_Location :
Atlanta, GA, USA
Print_ISBN :
978-1-4244-1709-4
Type :
conf
DOI :
10.1109/VLSISOC.2007.4402477
Filename :
4402477
Link To Document :
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