Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis

With shrinking feature sizes in deep sub-micron technologies, interconnect delays play a dominant role in the cycle time of digital circuits. It is essential to consider the impact of physical design during high-level synthesis. No prior work exists in literature that accounts for the topology of nets resulting from binding decisions during high-level synthesis. This paper presents a novel floorplan-aware high-level synthesis technique that uses accurate net topologies and distributed wire-delay models to guide resource allocation and binding decisions during design-space exploration. The proposed approach tightly integrates a floorplanner with a high-level synthesis binding algorithm. The location of data path modules in the floorplan is used to determine the minimal length RSMT of every net, to which the delay model is applied to accurately estimate delays of multi-terminal nets. Our results show that, when compared to previous approaches, the synthesis technique proposed in this paper reduces wire delays by as much as 48.9% in 70nm technology with an average improvement of 38.6%, and an overhead of only 3.6% in chip area