Suitable cache organizations for a novel biomedical implant processor

Author

Strydis, Christos

Author_Institution

Comput. Eng. Lab., Delft Univ. of Technol., Delft

fYear

2008

fDate

12-15 Oct. 2008

Firstpage

591

Lastpage

598

Abstract

This paper evaluates various instruction- and data-cache organizations in terms of performance, power, energy and area on a suitably selected biomedical benchmark suite. The benchmark suite consists of compression, encryption and data-integrity algorithms as well as real implant applications, all executed on biomedical input datasets. Results are used to drive the (micro)architectural design of a novel microprocessor targeting microelectronic implants. Our profiling study has revealed a L1 instruction-cache of 8 KB size (when relaxed area constraints are imposed) and a L1 data-cache of 4 KB size, both structured as 2-way associative caches, as optimal organizations for the envisioned implant processor.

Keywords

biomedical electronics; cache storage; content-addressable storage; cryptography; data compression; data integrity; microcomputers; prosthetics; 2 way associative cache; L1 data cache; L1 instruction cache; biomedical benchmark suite; biomedical implant processor; biomedical input datasets; data cache organization; data compression algorithm; data encryption algorithm; data integrity algorithm; instruction cache organization; memory size 4 KByte; memory size 8 KByte; micro-architectural design; microelectronic implants; microprocessor; Application software; Biomedical computing; Biomedical engineering; Circuits; Geometry; Microelectronic implants; Monitoring; Pacemakers; Power engineering and energy; Power engineering computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design, 2008. ICCD 2008. IEEE International Conference on

Conference_Location

Lake Tahoe, CA

ISSN

1063-6404

Print_ISBN

978-1-4244-2657-7

Electronic_ISBN

1063-6404

Type

conf

DOI

10.1109/ICCD.2008.4751921

Filename

4751921