2380240

2002 7th International Symposium on Plasma- and Process-Induced Damage (IEEE Cat. No.02TH8582)

2002

5-7 June 2002

DRAM chips; dielectric thin films; electrostatic discharge; integrated circuit interconnections; integrated circuit manufacture; integrated circuit reliability; integrated circuit technology; plasma materials processing; semiconductor device manufacture; semiconductor device reliability; semiconductor technology; surface treatment; Cu; DRAM product visions; NVM product visions; advanced integration; antenna rules; chip design constraints; circuit effects; damage mechanisms; dielectric degradation mechanism; electrical overstress; high-k materials; low-k BEOL processing; low-k/Cu interconnects; negative-bias-temperature instability; new gate dielectric materials; plasma-induced damage; process effects; process-induced damage; robust tool design; thin gate oxide characterization; tool characterization;

English

ieee

Plasma- and Process-Induced Damage, 2002 7th International Symposium on

Maui, HI, USA

0-9651577-7-6

conf

10.1109/PPID.2002.1042594

1042594