A fine-grain dynamic sleep control scheme in MIPS R3000

Author

Seki, N. ; Lei Zhao ; Kei, Jo ; Ikebuchi, D. ; Kojima, Yu. ; Yohei Hasegawa ; Amano, Hideharu ; Kashima, Tomoko ; Takeda, Shigeki ; Shirai, Tokimasa ; Nakata, Mitustaka ; Usami, Kimiyoshi ; Sunata, Tetsuya ; Kanai, Jun ; Namiki, Mitaro ; Kondo, Masaaki ;

Author_Institution

Keio Univ., Yokohama

fYear

2008

fDate

12-15 Oct. 2008

Firstpage

612

Lastpage

617

Abstract

A fine-grain dynamic power gating is proposed for saving the leakage power in MIPS R3000 by sleep control and applied to a processor pipeline. An execution unit is divided into four small units: multiplier, divider, shifter and other (CLU). The power of each unit is cut off dynamically, based on the operation. We tape-outed the prototype chip Geyser-0, which provides an R3000 Core with the power reduction technique, 16 KB caches and translation lookaside buffer (TLB) using 90 nm CMOS technology. The evaluation results of four benchmark programs for embedded applications show that 47% of the leakage power is reduced on average with 41% area overhead.

Keywords

CMOS digital integrated circuits; pipeline processing; CMOS technology; Geyser-0; MIPS R3000; R3000 Core; fine-grain dynamic sleep control scheme; leakage power reduction; processor pipeline; translation lookaside buffer; Agriculture; CMOS technology; Central Processing Unit; Circuits; Computer architecture; Delay; Logic; Power dissipation; Prototypes; Sleep;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design, 2008. ICCD 2008. IEEE International Conference on

Conference_Location

Lake Tahoe, CA

ISSN

1063-6404

Print_ISBN

978-1-4244-2657-7

Electronic_ISBN

1063-6404

Type

conf

DOI

10.1109/ICCD.2008.4751924

Filename

4751924