Title :
Parallelized radix-2 scalable Montgomery multiplier
Author :
Jiang, Nan ; Harris, David
Author_Institution :
Harvey Mudd College, 301 E. Twelfth St. Claremont, CA 91711, USA
Abstract :
This paper describes the FPGA implementation of a parallelized scalable radix-2 Montgomery multiplier. It improves upon previous designs by rearranging previously sequential calculations to take place in parallel. On a Virtex-II FPGA, this design can perform 1024-bit modular exponentiation in 6.3 ms using 6006 lookup tables, a 17 % speed improvement over the previously fastest scalable radix-2 Montgomery multiplier.
Keywords :
Algorithm design and analysis; Clocks; Costs; Cryptography; Delay; Educational institutions; Field programmable gate arrays; Hardware; Kernel; Table lookup;
Conference_Titel :
Very Large Scale Integration, 2007. VLSI - SoC 2007. IFIP International Conference on
Conference_Location :
Atlanta, GA, USA
Print_ISBN :
978-1-4244-1710-0
Electronic_ISBN :
978-1-4244-1710-0
DOI :
10.1109/VLSISOC.2007.4402488
