DocumentCode
2380377
Title
The 16 kB single-cycle read access cache on a next-generation 64 b Itanium microprocessor
Author
Bradley, D. ; Mahoney, P. ; Stackhouse, B.
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
110
Abstract
A 16 kB four-ported physically addressed cache to be placed on a 64 b Itanium microprocessor operates at 1.2 GHz with 19.2 GB/s peak bandwidth. Circuit and microarchitectural techniques are optimized to allow a single-cycle read access latency. The cache occupies 3.2×1.8 mm/sup 2/ in a 0.18 μm CMOS process.
Keywords
CMOS memory circuits; cache storage; microprocessor chips; 0.18 micron; 1.2 GHz; 16 kB; 64 bit; CMOS process; Itanium microprocessor; four-ported physically addressed cache; microarchitectural techniques optimisation; single-cycle read access latency; CADCAM; Circuits; Clocks; Computer aided manufacturing; Decoding; FETs; Microprocessors; Pipelines; Pulse generation; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.992963
Filename
992963
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