Test data compression and TAM design

Test Data Compression (TDC) techniques have been developed for reducing requirements in terms of Automatic Test Equipment resources. These techniques generally deal with stand alone circuits. In this paper, we explore the benefits of using TDC techniques in the context of core-based SoCs. TDC is used to reduce the test time by improving the parallelism of core tests without the expense of additional ATE channels. We first detail the constraints on test architectures and on the design flow inferred by the use of TDC. We propose a method for seeking an optimal architecture in terms of total test application time. The method is independent of the compression scheme used for reduction of core test data. The gain in terms of test application time for the SoC is over 50% compared to a test scheme without compression.