DocumentCode
2380512
Title
Direct digital frequency synthesizers using high-order polynomial approximation
Author
De Caro, D. ; Napoli, E. ; Strollo, A.G.M.
Author_Institution
Dept. of Electron. Eng., Naples Univ., Italy
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
134
Abstract
Two 80 MHz 0.35 /spl mu/m 3.3V CMOS ROM-less DDFS using polynomial approximation are compared with Cordic-based circuits. A 60 dBc SFDR DDFS uses 2nd-order polynomials and 0.18 mm/sup 2/, with 15 mW dissipation. An 80 dBc SFDR DDFS uses 3rd-order polynomials and 0.44 mm/sup 2/, with 35 mW dissipation.
Keywords
circuit CAD; direct digital synthesis; polynomial approximation; 0.35 /spl mu/m CMOS; 0.35 micron; 15 mW dissipation; 3.3 V; 3.3V; 35 mW dissipation; 60 dBc; 80 MHz; 80 dBc; Cordic algorithm; DDFS; Horner architectures; Wallace multiply accumulators; direct digital frequency synthesizers; high-order polynomial approximation; high-performance communication; hyper-folding technique; phase accumulator; sine/cosine generator; spurious-free dynamic range; Circuits; Communication switching; Dynamic range; Frequency control; Frequency synthesizers; Optimization methods; Polynomials; Power dissipation; Signal generators; Taylor series;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.992972
Filename
992972
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