• DocumentCode
    2380524
  • Title

    P2ID in a modern CMOS technology

  • Author

    Cellere, G. ; Valentini, M.G. ; Caminati, M. ; Paccagnella, A.

  • Author_Institution
    Dipt. di Elettronica e Inf., Padova Univ., Italy
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    72
  • Lastpage
    75
  • Abstract
    Plasma process induced damage has been widely investigated in the past few years. We present in this work results from a yearlong study intended to reduce plasma-induced damage in a modern CMOS technology, featuring ultra thin gate oxide. We studied both nMOSFETs and pMOSFETs with a physical gate oxide thickness of 3.5 nm.
  • Keywords
    CMOS integrated circuits; MOSFET; dielectric thin films; integrated circuit reliability; plasma materials processing; 3.5 nm; CMOS technology; P2ID; nMOSFETs; pMOSFETs; physical gate oxide thickness; plasma process induced damage; plasma-induced damage; ultra thin gate oxide; CMOS technology; Fingers; MOSFETs; Modems; Plasma applications; Plasma chemistry; Plasma density; Plasma devices; Plasma materials processing; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Plasma- and Process-Induced Damage, 2002 7th International Symposium on
  • Print_ISBN
    0-9651577-7-6
  • Type

    conf

  • DOI
    10.1109/PPID.2002.1042612
  • Filename
    1042612
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2380524