Title :
P2ID in a modern CMOS technology
Author :
Cellere, G. ; Valentini, M.G. ; Caminati, M. ; Paccagnella, A.
Author_Institution :
Dipt. di Elettronica e Inf., Padova Univ., Italy
Abstract :
Plasma process induced damage has been widely investigated in the past few years. We present in this work results from a yearlong study intended to reduce plasma-induced damage in a modern CMOS technology, featuring ultra thin gate oxide. We studied both nMOSFETs and pMOSFETs with a physical gate oxide thickness of 3.5 nm.
Keywords :
CMOS integrated circuits; MOSFET; dielectric thin films; integrated circuit reliability; plasma materials processing; 3.5 nm; CMOS technology; P2ID; nMOSFETs; pMOSFETs; physical gate oxide thickness; plasma process induced damage; plasma-induced damage; ultra thin gate oxide; CMOS technology; Fingers; MOSFETs; Modems; Plasma applications; Plasma chemistry; Plasma density; Plasma devices; Plasma materials processing; Testing;
Conference_Titel :
Plasma- and Process-Induced Damage, 2002 7th International Symposium on
Print_ISBN :
0-9651577-7-6
DOI :
10.1109/PPID.2002.1042612
