Low power on-chip thermal sensors based on wires

Current thermal scaling trends in multilevel low-k interconnect structures suggest an increasing heat density as we move from substrate to higher metal levels. Thus, the deterioration of interconnect performance at extreme temperatures has the capability to offset the degradation in device performance when operating at higher-than-normal temperatures. Existing thermal sensing approaches rely heavily on devices (MOS/diodes). They are optimized for a low area and power overhead but continue to suffer from leakage and self-heating and also, tend to disregard the thermal impact on interconnects. We propose an alternate approach of using interconnects to perform the thermal sensing. With feature-size shrinking, metal layers are closer to the substrate suggesting a strong correlation between interconnect temperature and thermal profile of the underlying substrate. Thus, in addition to quantifying the temperature impact on interconnect signal delay; output of proposed sensors can be used to estimate substrate thermal status as well. The simplistic schemes proposed allow reuse of existing on-chip resources such as drivers and time-digitizers, have a low power requirement and are robust against variations in wire dimensions, non-uniform temperature distribution and supply noise.