ULSI circuit design trend, technology road map, and test structures for process-induced damage

According to the exponential growth trend of Moore´s law, single system-on-chip (SOC) device with multi-billion transistors will be available within several years. However, there are several major questions that are worth considering: What should we do with these billion-transistor devices? Which circuit design technique and system architectures will support these devices? How should we solve the heat dissipating and noise problems generated by a billion transistors? Which transistor device structures are under the consideration? What are the potential device yield and reliability problems especially process-induced damage (PID) in manufacturing these SOC devices? In this paper, industry trends and some key issues related to these questions are reviewed with the consideration of PID.