Title :
A 16 mW 30 MSample/s 10 b pipelined A/D converter using a pseudo-differential architecture
Author :
Miyazaki, D. ; Furuta, M. ; Kawahito, S.
Author_Institution :
Graduate Sch. of Electron. Sci. & Technol., Hamamatsu, Japan
Abstract :
The authors present a 16 mW 2 V 30 MSample/s 10 b pipelined A/D converter in 0.3 /spl mu/m CMOS technology which uses a pseudo-differential architecture and a capacitor cross-coupled S/H stage. SNDR and the SFDR at 30 MHz input are 54 dB and 67 dB, respectively.
Keywords :
CMOS integrated circuits; analogue-digital conversion; high-speed integrated circuits; low-power electronics; pipeline processing; 0.3 micron; 10 bit; 16 mW; 2 V; CMOS technology; capacitor cross-coupled S/H stage; high SNDR; high-speed ADC; low-power design; low-power dissipation; pipelined A/D converter; pipelined ADC chip; pseudo-differential architecture; sample/hold stage; Broadband amplifiers; Capacitors; Frequency measurement; Pipelines; Power amplifiers; Power dissipation; Pulse amplifiers; Sampling methods; Switches; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.992992
