Device modeling of plastic transfer molding packaged bipolar transistors by use of 3D EM simulations

A method for extracting large signal models of packaged bipolar transistors is described. To circumvent difficulties resulting from complex parasitic surroundings of the inner transistor the modeling procedure has been separated in a number of parts. First of all the inner transistor (chip) was measured using an on wafer probable coplanar environment that could have been well modeled and has had less significant parasitics. The deembedded results were used to extract a Gummel Poon model of the inner transistor optimized for both, DC and RF parameters. The package including a coaxial environment, which has been proven to influence the electrical characteristic least, has been computed using a 3D EM simulator based on the FDTD method. The results, considering all coupling effects, have then been used to extract an equivalent circuit of the package. A transistor chip model and package EC are available for the circuit simulation techniques and compare well to corresponding measured results