Title :
A 1.8 V 14 b /spl Delta//spl Sigma/ A/D converter with 4MSamples/s conversion
Author :
Ruoxin Jiang ; Fiez, T.S.
Author_Institution :
Oregon State Univ., Corvallis, OR, USA
Abstract :
A fifth-order single-stage ΔΣ modulator achieves 14 b resolution with 8× OSR and 4 MHz conversion bandwidth in a 1.8 V 0.18 μm CMOS process. The DC gain of the internal op amps is 43 dB. It occupies 1.3×2.2 mm/sup 2/ and consumes 102 mW analog power and 47 mW digital power.
Keywords :
CMOS integrated circuits; analogue-digital conversion; delta-sigma modulation; switched capacitor networks; /spl Delta//spl Sigma/ A/D converter; /spl Delta//spl Sigma/ ADC; 1.8 V; 14 bit; 150 mW; 18 micron; LV submicron CMOS processes; SC modulator; delta-sigma ADC; double-poly five-metal CMOS process; fifth-order delta-sigma modulator; single-stage /spl Delta//spl Sigma/ modulator; switched-capacitor modulator; Bandwidth; Baseband; CMOS process; Clocks; Delay; Delta modulation; Linearity; Quantization; Semiconductor device noise; Signal to noise ratio;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.993015
