DocumentCode
2381707
Title
Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits
Author
Badaroglu, M. ; van Heijningen, M. ; Gravot, V. ; Compiet, J. ; Donnay, S. ; Engels, M. ; Gielen, G. ; De Man, H.
Author_Institution
IMEC, Leuven, Belgium
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
274
Abstract
An efficient substrate-noise-reduction technique for synchronous CMOS circuits shows >2/spl times/ noise reduction with penalties of 3% area and 4% power increase in a 5k-gate synchronous CMOS circuit fabricated in a 0.35 /spl mu/m CMOS process on an epi-type substrate.
Keywords
CMOS integrated circuits; integrated circuit design; integrated circuit noise; integrated circuit testing; interference suppression; mixed analogue-digital integrated circuits; 0.35 micron; CMOS mixed-signal ICs; CMOS process; epi-type substrate; noise reduction area penalties; noise reduction power penalties; substrate noise reduction; synchronous CMOS circuits; synchronous digital circuits; CMOS logic circuits; Circuit noise; Current supplies; Delay; Digital circuits; Energy consumption; Noise generators; Noise measurement; Noise reduction; Rails;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.993042
Filename
993042
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