The CRAY Y-MP: a user´s viewpoint

Author

Stevens, K.G., Jr. ; Sykora, Ron

Author_Institution

NASA Ames Res. Center, Moffett Field, CA, USA

fYear

1990

fDate

Feb. 26 1990-March 2 1990

Firstpage

12

Lastpage

15

Abstract

The significant hardware and software aspects of the first CRAY Y-MP system to be delivered are described. Performance comparisons are made with other Cray products, and the overall system configuration into which the CRAY Y-MP was integrated are described. The CRAY Y-MP mainframe has eight CPU modules implemented with 2500-gate macrocell array logic chips and 32 memory modules made with the same logic chips and with emitter-coupled-logic-compatible RAM chips. A 1.56-billion-operations-per-second speed was achieved for a general sparse matrix factorization algorithm, which was applied to solve the statics problem for several large-scale finite-element models. It has demonstrated an availability of 96.8%. The multiprocessing tools provided with the system and the system performance and configuration are discussed.<>

Keywords

computer architecture; mainframes; 1.56 GIPS; CPU modules; CRAY Y-MP mainframe; availability; emitter-coupled-logic-compatible RAM chips; finite-element models; macrocell array logic chips; memory modules; multiprocessing tools; sparse matrix factorization algorithm; statics problem; system configuration; system performance; Availability; Finite element methods; Hardware; Large-scale systems; Logic arrays; Macrocell networks; Random access memory; Read-write memory; Sparse matrices; System performance;

fLanguage

English

Publisher

ieee

Conference_Titel

Compcon Spring '90. Intellectual Leverage. Digest of Papers. Thirty-Fifth IEEE Computer Society International Conference.

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-8186-2028-5

Type

conf

DOI

10.1109/CMPCON.1990.63646

Filename

63646