DocumentCode
2381821
Title
A 2.4 GHz 0.18 /spl mu/m CMOS self-biased cascode power amplifier with 23 dBm output power
Author
Sowlati, T. ; Leenaerts, D.
Author_Institution
Philips Res.-USA, Briarcliff Manor, NY, USA
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
294
Abstract
A two-stage self-biased cascode power amplifier in 0.18 /spl mu/m CMOS process for Class 1 Bluetooth application provides 23 dBm output power with 31 dB gain and 42% PAE at 2.4 GHz. The power amplifier die occupies 0.46 mm/sup 2/.
Keywords
CMOS analogue integrated circuits; UHF integrated circuits; UHF power amplifiers; 0.18 micron; 2.4 GHz; 31 dB; 42 percent; CMOS two-stage self-biased cascode power amplifier; Class 1 Bluetooth application; die area; gain; output power; power added efficiency; Bluetooth; CMOS technology; Capacitors; Degradation; Hot carriers; Power amplifiers; Power generation; Radio frequency; Radiofrequency amplifiers; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.993048
Filename
993048
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