DocumentCode
2382125
Title
Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading
Author
Preston, R.P. ; Badeau, R.W. ; Bailey, D.W. ; Bell, S.L. ; Biro, L.L. ; Bowhill, W.J. ; Dever, D.E. ; Felix, S. ; Gammack, R. ; Germini, V. ; Gowan, M.K. ; Gronowski, P. ; Jackson, D.B. ; Mehta, S. ; Morton, S.V. ; Pickholtz, J.D. ; Reilly, M.H. ; Smith,
Author_Institution
Compaq Comput. Corp., Shrewsbury, MA, USA
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
334
Abstract
A 250M transistor microprocessor implements the Alpha instruction set and features 8-wide superscalar issue and simultaneous multithreading in a 0.125/spl mu/m SOI process. Performance is estimated at over three times that of the previous design.
Keywords
microprocessor chips; multi-threading; reduced instruction set computing; silicon-on-insulator; 0.125 micron; Alpha instruction set; SOI process; simultaneous multithreading; superscalar RISC microprocessor; CMOS process; CMOS technology; Central Processing Unit; Computer aided instruction; Microprocessors; Multithreading; Out of order; Reduced instruction set computing; Surface-mount technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.993068
Filename
993068
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