Title :
The implementation of the next-generation 64 b Itanium/sup TM/ microprocessor
Author :
Naffziger, S.D. ; Hammond, G.
Author_Institution :
Hewlett-Packard Co., Fort Collins, CO, USA
Abstract :
The authors present the 64 bit Itanium/spl trade/ microprocessor, which incorporates over 220M transistors on a 465 mm/sup 2/ die and operates at >1.2 GHz with an 8-stage pipeline in a 0.18 /spl mu/m process. It has three levels of on-chip cache totaling over 3.3 MB providing >32 GB/s bandwidth at each level.
Keywords :
CMOS digital integrated circuits; VLSI; high-speed integrated circuits; microprocessor chips; parallel architectures; pipeline processing; 0.18 micron; 1.2 GHz; 3.3 MB; 64 bit; CMOS process technology; Itanium microprocessor; eight-stage pipeline; integer operations; memory system; micro-architecture; on-chip cache; parallel execution; Bandwidth; Delay; Frequency; Hardware; History; Integrated circuit interconnections; Microprocessors; Pipelines; Registers; Shape;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.993073
