Failure analysis using IDD current leakage and photo localization for gate oxide defect of CMOS VLSI

The typical electrical degradation on the complementary metal oxide semiconductor (CMOS) performance is due to defect in gate oxide layer. During integrated circuit (IC) infant mortality phase, stress tests introduced at wafer sort and final test in order to assured only good IC being deliver to end customer. Stress tests such as burn-in, gate stress, and quiescent current (IDDQ) test, demonstrated their competency to screen out this type of early failure. Nevertheless, the latent defect is a time dependent failure, which, affect the CMOS reliability after certain time, temperatures and application stress. Consequently, revise failure analysis technique has to be introduced in effective approach to compensate the problem in the current technology due to metal interconnection layers and dense for front side failure analysis (FA). The motivation of this work is to present the fault localization on the elevated IDD current of the faulty logic cells during the transition by photo localization technique and clarify gate oxide defect through circuit simulation. We have confirmed that the IDD scan test and photo localization technique were effective to localize faulty IC in silicon active area through front side.