Implementation of arbitrary circuits using modified constant delay technique

This paper perceives Pre evaluation of output before the arrival of inputs from the preceding stagesis ready becomes an added advantage of MCD logic style. Besides adjusting the width of timing window, clock allocation and its distribution are considered as crucial design factors. Power consumption is drasticallyreduced, but the pre-charge propagation path delay affects the speed performances and limits the energy-delay product (EDP) improvement. Using 45-nm general purpose CMOS technology, MCD logic is evaluated for single cycle multi-staged circuit block. Simulation results unveil that the MCD logic achieves meliorate performance and is more energy efficient than the other logic styles for the implementation on arbitrary circuits.