A 6.5 GHz 130 nm single-ended dynamic ALU and instruction-scheduler loop

Author

Anders, M. ; Mathew, S. ; Bloechel, B. ; Thompson, S. ; Krishnamurthy, R. ; Soumyanath, K. ; Borkar, S.

Author_Institution

Microprocessor Res. Labs, Intel Corp., Hillsboro, OR, USA

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

410

Abstract

32b Han-Carlson ALU and 8-entry /spl times/ 2-ALU instruction scheduler loop for 6.5 GHz single-cycle integer execution at 1.2 V and 25/spl deg/C uses dual-Vt CMOS technology. A single-ended, leakage-tolerant dynamic scheme enables up to 9-wide ORs with 23% critical path speed improvement, 40% active leakage power reduction compared to Koggie-Stone implementation, dense layout occupying 44, 100 /spl mu/m/sup 2/, and performance scalable to 8 GHz at 1.5 V, 25/spl deg/C.

Keywords

CMOS logic circuits; digital arithmetic; leakage currents; low-power electronics; processor scheduling; 1.2 V; 130 nm; 25 degC; 32 bit; 6.5 GHz; Han-Carlson ALU; active leakage power reduction; critical path speed improvement; dense layout; dual-Vt CMOS technology; instruction-scheduler loop; leakage-tolerant dynamic scheme; single-cycle integer execution; single-ended dynamic ALU; Active noise reduction; Adders; CMOS technology; Circuit noise; Logic circuits; MOS devices; Microprocessors; Out of order; Power dissipation; Processor scheduling;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.993106

Filename

993106