Design of high speed Sense Amplifier for SRAM

Author

Chandankhede, Rakesh Dayaramji ; Acharya, Debiprasad Priyabrata ; Patra, Pradip Kumar

Author_Institution

Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Rourkela, India

fYear

2014

fDate

8-10 May 2014

Firstpage

340

Lastpage

343

Abstract

1kb static random access memory (SRAM) is designed and tested for correct read and write operation. Novel Sense Amplifier (SA) circuit for 1kb SRAM are presented and analysed in this paper. Sense amplifier using decoupled latch with current controlled architecture is proposed and compared with Current controlled latch SA using 90nm CMOS technology. Delay and power dissipation in proposed SA is 21.5% and 18.5% less than that of current controlled SA. The maximum operating frequency of the SRAM is found as 1.25GHz.

Keywords

CMOS integrated circuits; SRAM chips; UHF amplifiers; electric current control; flip-flops; high-speed integrated circuits; CMOS technology; SRAM; correct read; current controlled latch SA circuit; decoupled latch; delay dissipation; frequency 1.25 GHz; high speed sense amplifier design; maximum operating frequency; memory size 1 KByte; power dissipation; size 90 nm; static random access memory; write operation; CMOS integrated circuits; CMOS technology; Delays; Random access memory; Robustness; Transistors; Cache memory; SRAM architecture; Sense Amplifier; current controlled SA;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Communication Control and Computing Technologies (ICACCCT), 2014 International Conference on

Conference_Location

Ramanathapuram

Print_ISBN

978-1-4799-3913-8

Type

conf

DOI

10.1109/ICACCCT.2014.7019459

Filename

7019459