Implementing a partial group based routing for homogeneous fat tree network on chip architecture

As the growing consumer electronic market imposes constraint such as compact product design and strict time to market, the traditional method of chip designing failed miserably to satisfy these constraints. With the evolution of Network-on-Chip, researchers have made an honest effort to resolve such issues but designing a network which encourages reusability of components and also scalable still remains an area where more refinement is necessary. In this paper we present before you a fat tree based network on chip. The entire design of the network with the nodes and switches has been described in details. The proposed architecture has been implemented and analyzed in a C++ based simulator. The analysis results have been presented at the end of the paper.