An embedded merging scheme for VLSI implementation of H.264/AVC motion estimation modules

The variable block size motion estimation (VBSME) technique can improve the coding efficiency greatly and has been adopted into the latest international video coding standard H.264/AVC. However, the VBSME technique introduces excessive computations comparing to fix block size ones. In H.264/AVC, the possible macroblock partition modes can have up to 259 different combinations, which make the design of an efficient VLSI architecture for H.264/AVC a challenging task. Many VLSI designs for the general motion estimation modules were presented in past decades, and some of them were also implemented as commercial products. Thereby, instead of developing a newly motion estimation module for H.264/AVC, this paper proposes an embedded merging scheme to extend the applicability of existing VLSI architectures. More specifically, the proposed embedded merging scheme only adds a few components into the existing VLSI architecture modules but can empower them to deal with the new H.264/AVC applications.