DocumentCode
2383516
Title
Design, simulation, and fabrication of a new poly-Si based capacitor-less 1T-DRAM cell
Author
Chen, Yun-Ru ; Lin, Jyi-Tsong ; Chang, Tzu-Feng ; Eng, Yi-Chuen ; Lin, Po-Hsieh ; Chen, Cheng-Hsin
Author_Institution
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
fYear
2012
fDate
13-16 May 2012
Firstpage
85
Lastpage
88
Abstract
In this paper, we propose a new fabrication method to form a polysilicon thin-film transistor with a smiling SiO2 layer. The experimental results suggest that the short-channel effects can be significantly reduced because the trench oxide is utilized to block the drain electric field. Furthermore, the so-called S/D tie can help to overcome the self-hating for enhancing the thermal reliability. And the device fabrication process is fully compatible with current conventional CMOS technology.
Keywords
DRAM chips; reliability; silicon compounds; thin film transistors; S-D tie; SiO2; current conventional CMOS technology; drain electric field; fabrication method; poly Si based capacitor-less 1T-DRAM cell; polysilicon thin-film transistor; thermal reliability; trench oxide; Doping; Fabrication; Performance evaluation; Sensors; Silicon; Thin film transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics (MIEL), 2012 28th International Conference on
Conference_Location
Nis
ISSN
pending
Print_ISBN
978-1-4673-0237-1
Type
conf
DOI
10.1109/MIEL.2012.6222802
Filename
6222802
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